1. Field of Invention
The present invention relates to a method of fabricating semiconductor circuit structures. More particularly, the present invention relates to a method for analyzing deep trench (DT) capacitors and a preparation method thereof.
2. Description of Related Art
With increases in the density of semiconductor integrated circuits (IC), the dimensions of semiconductor devices have decreased. One method for densifying the integration of semiconductor integrated circuits is to use trench capacitors. However, many structural defects occur when manufacturing the trench capacitors, causing many problems in the semiconductor integrated circuits.
A conventional structural analysis method for trench capacitors is to use a focused ion beam (FIB) to mill the overlying circuits on a die layer-by-layer from the top to the bottom. An inspection using an electron microscope is performed on every layer. However, since the dimensions of these trench capacitors are quite small, the overlying circuits are easily over-milled. Consequently, the structural defects are often milled away before they can be inspected, making the ability to detect such structural defects more challenging.
Recently, U.S. Pat. No. 6,403,439 has disclosed a structural analysis method for deep trench capacitors. First, chemical mechanical polishing (CMP) is performed to remove the first part from the backside of the substrate. Then, a chemical etchant is used to remove the remainder of the substrate, leaving the three-dimensional structures of the deep trench capacitors exposed to facilitate structural analysis. However, this method entails removing a lot of material. Furthermore, the removal depth of the CMP is not easy to control; hence, the deep trench structure is easily destroyed.